1. Field
Example embodiments of the inventive concepts relate to semiconductor devices and methods of fabricating the same, and more particularly, to three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells and methods of fabricating the same.
2. Description of the Related Art
A 3D-IC memory technique may be used for increasing a memory capacity. 3D-IC memory technique refers generally to technologies related to arranging memory cells three-dimensionally. In addition to a 3D-IC memory technique, a memory capacity may be increased through (1) a pattern miniaturization technique; and (2) a multi-level cell (MLC) technique. However, the use of a pattern miniaturization technique may be limited due to high cost and the capacity increase achieved by the MLC technique may be limited to the number of bits to be increased in each cell. The pattern miniaturization technique and the MLC techniques may be combined with the 3D-IC technique, in terms of realizing a more increased memory capacity, and may be expected to develop separately from the 3D-IC technique.
One 3D-IC technique is a punch-and-plug technique. The punch-and-plug technique includes sequentially forming multi-layered thin layers on a substrate and then forming plugs to penetrate the thin layers. Through this technique, without a drastic increase of manufacturing costs, a memory capacity of a three-dimensional memory device may be achieved.